1. Field of the Invention
The present invention relates to a semiconductor device, and especially relates to the semiconductor device capable of detecting malfunction.
2. Description of the Background Art
In the semiconductor device, for reason of various dispersions, there is also the dispersion in a path delay having a certain memory element as an end point. The path delay operates without problem in a simulation, however, in an actual device, there has been a case in which a timing constraint (setup violation) is not satisfied due to the dispersion by the path delay and this does not operate.
Therefore, there has been a case to provide a mechanism for actively detecting the timing constraint in the semiconductor device. As such a mechanism, a circuit, so-called, Razor (hereinafter, referred to as a Razor circuit) disclosed in Dan Ernest, et al., “Razor: Low-Power Pipeline Based on Circuit-Level Timing Speculation”, IEEE MICRO, 2004, pp. 10-20 is known. The Razor circuit disclosed in Dan Ernest, et al., “Razor: Low-Power Pipeline Based on Circuit-Level Timing Speculation”, IEEE MICRO, 2004, pp. 10-20 is obtained by combining a flip-flop circuit for capturing data in synchronization with a rising edge of a clock signal clk and a latch circuit for capturing data in a High period of the clock signal clk. In addition, the Razor circuit has compared an output of the flip-flop circuit with that of the latch circuit by a comparator to switch the output of the flip-flop circuit, which is the general logic, and that of the latch circuit, by a selector circuit, based on the comparison result.
In the Razor circuit disclosed in Dan Ernest, et al., “Razor: Low-Power Pipeline Based on Circuit-Level Timing Speculation”, IEEE MICRO, 2004, pp. 10-20, the latch circuit opens in synchronization with timing with which the flip-flop circuit captures data, and the latch circuit captures the data during the High period of the clock signal clk. That is to say, the Razor circuit disclosed in Dan Ernest, et al., “Razor: Low-Power Pipeline Based on Circuit-Level Timing Speculation”, IEEE MICRO, 2004, pp. 10-20 detects the data reaching from rising of the clock signal clk until the High period of the clock signal clk as the malfunction (setup violation) by using a time difference between the flip-flop circuit and the latch circuit.
Next, in the U.S. Pat. No. 6,985,547, two sub synchronous circuits having the same configuration as that of a main synchronous circuit are provided, and the sub synchronous circuits have circuit configuration to operate at double periods of the main synchronous circuit. Therefore, the circuit disclosed in the U.S. Pat. No. 6,985,547 may restore the malfunction of the setup violation generated in the main synchronous circuit by the sub synchronous circuit.
Next, in the Japanese Patent Application Laid-Open No. 2005-214732, a combination logic circuit is interposed between a sending flip-flop circuit and a receiving flip-flop circuit, being operated by the same clock signal clk, as a critical path. In addition, in the Japanese Patent Application Laid-Open No. 2005-214732, the delay condition in the critical path is calculated and is displayed on an outer portion of the semiconductor device.
In order to specify the point at which the setup violation occurs, by providing a plurality of circuits in the semiconductor device disclosed in Dan Ernest, et al., “Razor: Low-Power Pipeline Based on Circuit-Level Timing Speculation”, IEEE MICRO, 2004, pp. 10-20, it has been required to pick up the error signal output from each circuit. However, although a plurality of pins are required for picking up the error signal, the number of pins of the semiconductor device is limited, so that it has been general to bundle the error signals output from the circuits disclosed in Dan Ernest, et al., “Razor: Low-Power Pipeline Based on Circuit-Level Timing Speculation”, IEEE MICRO, 2004, pp. 10-20 by an OR tree. Therefore, the conventional semiconductor device has had a problem that it is not possible to specify the point at which the setup violation occurs.
Also, in the circuits disclosed in Dan Ernest, et al., “Razor: Low-Power Pipeline Based on Circuit-Level Timing Speculation”, IEEE MICRO, 2004, pp. 10-20, U.S. Pat. No. 6,985,547 and Japanese Patent Application Laid-Open No. 2005-214732, even if the setup violation is detected and the condition of the setup violation is restored, there has been a case in which the malfunction is induced in a subsequent stage.
Further, the condition to detect the setup violation in the semiconductor device is not constant and there is dispersion. Therefore, there has been a problem that there is a circuit in which the setup violation is not detected if one condition is fixed.